High Performance Communication Protocols Integrated with Adaptive Signal Processing Engines for Scalable Multi Core Architectures
DOI:
https://doi.org/10.66472/casp.v1i1.34Keywords:
Multi-core systems, Communication protocols, Signal processing, Data throughput, Network-on-ChipAbstract
This study investigates the integration of high performance communication protocols with adaptive signal processing engines in multi-core systems, aiming to enhance scalability, throughput, and inter-core communication efficiency. The challenges inherent in traditional multi core architectures, such as communication overhead, latency, and scalability limitations, are addressed through the incorporation of Network-on-Chip (NoC) architectures and adaptive signal processing techniques. By using a multi-core digital signal processing (DSP) platform, the study evaluates the performance improvements achieved by this integration under varying workloads and core configurations. The experimental results show a 35% improvement in throughput and a 25% reduction in communication latency, highlighting the effectiveness of adaptive communication protocols in managing data traffic between cores and reducing bottlenecks. The integration of NoC architecture facilitates parallel data transfers, while adaptive signal processing engines ensure that data flows more efficiently across the cores, enhancing system responsiveness, especially under high data rate conditions. Furthermore, the study explores the scalability of the proposed system, demonstrating its ability to maintain high performance as core counts increase. The findings emphasize the potential of combining advanced communication protocols with adaptive signal processing for optimizing multi-core system performance. Practical implications of this research include the design of scalable, flexible, and efficient multi core architectures suitable for complex, data-intensive applications. Future research should focus on further refining communication protocols and exploring additional integration strategies to enhance the adaptability and scalability of multi-core systems in next-generation computing environments.
References
[1] R. Mishra, I. Ahmad, and A. Sharma, “A dynamic multi-threaded queuing mechanism for reducing the inter-process communication latency on multi-core chips,” in Proceedings - 2020 3rd International Conference on Data Intelligence and Security, ICDIS 2020, 2020, pp. 12 – 19. doi: 10.1109/ICDIS50059.2020.00008.
[2] T. Guertin and A. Hurson, “The multicore architecture,” Adv. Comput., vol. 130, pp. 139 – 162, 2023, doi: 10.1016/bs.adcom.2022.09.003.
[3] A. Ailamaki, E. Liarou, P. Tözün, D. Porobic, and I. Psaroudakis, “How to stop under-utilization and love multicores,” in Proceedings - International Conference on Data Engineering, 2015, pp. 1530 – 1533. doi: 10.1109/ICDE.2015.7113419.
[4] M. R. V. S. R. S. Reddy, S. R. Raju, K. K. Girish, and B. Bhowmik, “Performance Analysis and Predictive Modeling of MPI Collective Algorithms in Multi-Core Clusters: A Comparative Study,” Int. Conf. Commun. Syst. Networks, COMSNETS, no. 2025, pp. 448 – 455, 2025, doi: 10.1109/COMSNETS63942.2025.10885723.
[5] D. Danang and Z. Mustofa, “CLSTMNet Architecture: A CNN–LSTM-Based Hybrid Deep Learning Model for DDoS Attack Detection and Mitigation in Network Security,” J. Artif. Intell. Technol., 2026.
[6] E. Siswanto, D. Danang, I. Kusumaningroem, and I. Akhsani, “Assessing Software Architecture Resilience Using Quantitative Metrics in Cloud Native Application Development Environments,” Indones. J. Infomatics, vol. 1, no. 1, pp. 11–21, 2026.
[7] Danang, T. Wahyono, I. Sembiring, T. Wellem, and N. H. Dzulkefly, “An Adaptive Framework Integrating ML Blockchain and TEE for Cloud Security,” in Proceeding - 2025 4th International Conference on Creative Communication and Innovative Technology: Empowering Transformative MATURE LEADERSHIP: Harnessing Technological Advancement for Global Sustainability, ICCIT 2025, 2025. doi: 10.1109/ICCIT65724.2025.11167152.
[8] Q. Xu and X. Yang, “Asynchronous Dual-Thread Communication Module with Parent/Children Resource Management in Multi-core Architecture,” in Proceedings - 2016 8th International Conference on Computational Intelligence and Communication Networks, CICN 2016, 2017, pp. 557 – 565. doi: 10.1109/CICN.2016.115.
[9] A. B. Rathod and S. M. Gulhane, “Performance Analysis of Multi-Core Systems in Multistage Interconnection Networks: Investigating Challenges in Inter-Processor Communication,” Panam. Math. J., vol. 34, no. 4, pp. 514 – 531, 2024, doi: 10.52783/pmj.v34.i4.2022.
[10] D. Danang, M. U. Dewi, and G. Widhiati, “Federated Hybrid CNN GRU and COBCO Optimized Elman Neural Network for Real Time DDoS Detection in Cloud Edge Environments,” Int. J. Electr. Eng. Math. Comput. Sci., vol. 2, no. 2, pp. 28–35, 2025, doi: https://doi.org/10.62951/ijeemcs.v2i2.293.
[11] D. Danang and Z. Mustofa, “Digital Forensics and Automated Incident Response Framework Leveraging Big Data Analytics and Real Time Network Traffic Profiling in Heterogeneous Cyber Environments,” Cyber Secur. Netw. Manag., vol. 1, no. 1, pp. 44–45, 2026.
[12] D. Danang, E. Siswanto, W. Aryani, and P. Wibowo, “Hybrid Federated Ensemble Learning Approach for Real-Time Distributed DDoS Detection in IIoT Edge Computing Environment,” J. Eng. Electr. Informatics, vol. 5, no. 1, pp. 9–17, 2025, doi: https://doi.org/10.55606/jeei.v5i1.5099.
[13] Z. Liu and H. Li, “Advanced Network-on-Chip (NoC) architectures for scalable multi-core systems,” IEEE Trans. Parallel Distrib. Syst., vol. 33, no. 5, pp. 1079–1091, 2022, doi: https://doi.org/10.1109/TPDS.2021.3094827.
[14] J. Wu and Q. Zhang, “Adaptive interconnection networks in multi-core systems: A survey,” Futur. Gener. Comput. Syst., vol. 83, pp. 251–266, 2018, doi: https://doi.org/10.1016/j.future.2017.09.002.
[15] L. Zhang, Y. Chen, and X. Liang, “High-performance interconnect solutions for multi-core processors in future computing systems,” J. Comput. Sci. Technol., vol. 36, no. 2, pp. 215–227, 2021, doi: https://doi.org/10.1007/s11390-021-0732-2.
[16] R. Patel and P. Kumari, “Nanophotonic interconnects for future multi-core architectures: Challenges and opportunities,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 15, no. 1, pp. 50–63, 2025, doi: https://doi.org/10.1109/JETCAS.2024.2995360.
[17] D. Danang, H. Haryani, Q. Aini, F. A. Ramahdan, and J. Edwards, “Empowering Digital Literacy Through Blockchain Based Alphasign for Secure and Sustainable E-Governance,” 2025.
[18] C.-A. Mosqueda-Arvizu, J.-A. Romero-González, D.-M. Córdova-Esparza, J. Terven, R. Chaparro-Sánchez, and J. Rodríguez-Reséndiz, “Logical Execution Time and Time-Division Multiple Access in Multicore Embedded Systems: A Case Study,” Algorithms, vol. 17, no. 7, 2024, doi: 10.3390/a17070294.
[19] M. N. Akhtar, Q. Azam, T. A. Almohamad, J. Mohamad-Saleh, E. A. Bakar, and A. A. Janvekar, “An Overview of Multi-Core Network-on-Chip System to Enable Task Parallelization Using Intelligent Adaptive Arbitration,” Lect. Notes Mech. Eng., pp. 15 – 38, 2021, doi: 10.1007/978-981-16-0866-7_2.
[20] D. Danang, A. B. Santoso, and M. U. Dewi, “CICA Framework: Harnessing CSR, AI, and Blockchain for Sustainable Digital Culture,” Int. J. Adv. Comput. Sci. & Appl., vol. 16, no. 11, 2025.
[21] D. Danang, N. D. Setiawan, and E. Siswanto, “Pemanfaatan Teknologi Internet of Things untuk Monitoring Kualitas Air Sungai di Wilayah Perkotaan,” J. New Trends Sci., vol. 2, no. 1, pp. 23–34, 2024.
[22] A. Ailamaki, “Databases and hardware: The beginning and sequel of a beautiful friendship,” Proc. VLDB Endow., vol. 8, no. 12 12, pp. 2058 – 2061, 2015, doi: 10.14778/2824032.2824142.
[23] D. Danang, E. Siswanto, N. D. Setiawan, and P. Wibowo, “Hybrid Zero Trust Container Based Model for Proactive Service Continuity under Intelligent DDoS Attacks in Cloud Environment,” Int. J. Comput. Technol. Sci., vol. 2, no. 3, pp. 41–49, 2025, doi: https://doi.org/10.62951/ijcts.v2i3.291.
